Tony Lindgren's "LC15: Fix flakey ddr3 detection with ref_ctrl and
ref_ctrl_final" assumes that 802bb57a584d also affects OMAP5 but it
doesn't, which means slower out-of-spec refresh rate is left at the
end and .ref_ctrl_final is never written. Let's write it out.
It is also good idea to set EMIF_REG_INITREF_DIS_MASK (like dra7 code
does) because otherwise a write to TIMING1 will start initialization
sequence (as documentation states) before other registers are
programmed.
Tested on 2GB and 4GB boards.
Signed-off-by: Grazvydas Ignotas <notasas(a)gmail.com>
---
arch/arm/cpu/armv7/omap-common/emif-common.c | 14 ++++++++------
arch/arm/cpu/armv7/omap5/sdram.c | 5 +++++
2 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 912db800ad..f43609103d 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -176,10 +176,7 @@ void emif_update_timings(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
- if (!is_dra7xx())
- writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
- else
- writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl_shdw);
+ writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl_shdw);
writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
@@ -387,7 +384,8 @@ static void omap5_ddr3_init(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
- writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
+ writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK,
+ &emif->emif_sdram_ref_ctrl);
writel(regs->sdram_config_init, &emif->emif_sdram_config);
/*
* Set SDRAM_CONFIG and PHY control registers to locked frequency
@@ -403,12 +401,16 @@ static void omap5_ddr3_init(u32 base, const struct emif_regs *regs)
writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
+ writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
+ writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
writel(regs->sdram_config_init, &emif->emif_sdram_config);
do_ext_phy_settings(base, regs);
- writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
+ __udelay(1000);
+ writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl);
+
omap5_ddr3_leveling(base, regs);
}
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 684467cb5f..bd86b0d9cb 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -36,6 +36,7 @@ const struct emif_regs emif_regs_532_mhz_2cs = {
.sdram_config_init = 0x80800EBA,
.sdram_config = 0x808022BA,
.ref_ctrl = 0x0000081A,
+ .ref_ctrl_final = 0x0000081A,
.sdram_tim1 = 0x772F6873,
.sdram_tim2 = 0x304a129a,
.sdram_tim3 = 0x02f7e45f,
@@ -55,6 +56,7 @@ const struct emif_regs emif_regs_532_mhz_2cs_es2 = {
.sdram_config_init = 0x80800EBA,
.sdram_config = 0x808022BA,
.ref_ctrl = 0x0000081A,
+ .ref_ctrl_final = 0x0000081A,
.sdram_tim1 = 0x772F6873,
.sdram_tim2 = 0x304a129a,
.sdram_tim3 = 0x02f7e45f,
@@ -74,6 +76,7 @@ const struct emif_regs emif_regs_266_mhz_2cs = {
.sdram_config_init = 0x80800EBA,
.sdram_config = 0x808022BA,
.ref_ctrl = 0x0000040D,
+ .ref_ctrl_final = 0x0000040D,
.sdram_tim1 = 0x2A86B419,
.sdram_tim2 = 0x1025094A,
.sdram_tim3 = 0x026BA22F,
@@ -94,6 +97,7 @@ const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
.sdram_config = 0x61851B32,
.sdram_config2 = 0x0,
.ref_ctrl = 0x00001035,
+ .ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x027F88A8,
@@ -118,6 +122,7 @@ const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
.sdram_config = 0x61851B32,
.sdram_config2 = 0x0,
.ref_ctrl = 0x00001035,
+ .ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x027F88A8,
--
2.17.1