28nm Manufacturing Process - The End of FD-SOI?

[dopefish]

So I noticed that the TI-OMAP5 CPU uses a 28nm process in its design. Although 28nm is quite a ways more efficient than the 45nm process from the OMAP4, it appears that in order to have smaller process sizes, FinFET would need to be used going forward, as FD-SOI is just not going to work all that well for anything lower than 28nm. Would anyone agree with that or is the older SOI manufacturing process possibly able to push the nm size boundaries further?

 

[Exophase]

I'm not sure what you're saying here. FD-SOI is a new technology, there are no chips on the market that use it. The only products I'm aware of that have even been announced to use FD-SOI are from ST, the developers of the 28nm FD-SOI process. On the other hand, Samsung has announced that they will offer an FD-SOI variant of their 28nm process, so there is probably some kind of customer base for it. There have also been mentions of FD-SOI extending down to 20nm and 14nm, but who knows what will happen...

Some earlier processes used PD-SOI, but most don't (including anything from Intel or TSMC) - they use "bulk" processes instead. Past AMD products made at Global Foundries (their big CPU product lines) used PD-SOI, but even they are transitioning to bulk; the 28nm Kaveri is made on a bulk process.

As for needing FinFET below 28nm, TSMC, Samsung, and Global Foundries are all doing 20nm processes that don't incorporate FinFETs. But they don't offer as much of a performance advantage as earlier shrinks do, which is why they're transitioning to processes that incorporate FinFETs soon after - the ones they call 16nm or 14nm are actually using the same back-end-of-line geometry as the 20nm process, so they're not much denser.

 

[TrashyMG]

Well yeah FinFET's have greatly improved power consumption, Were I work we attempted a 22nm without FinFETs and it ended up with horrible power consumption issues... the ASIC and Custom Logic division I work for decided to skip that technology and we now have use FinFETs in our new 14nm process. 

The issue is no other SoC manufacturer other than Ti seems to be giving EvilDragon a chance and I'm not sure what other company has delivered a product with FinFETs yet.

 

[Exophase]

The issue is no other SoC manufacturer other than Ti seems to be giving EvilDragon a chance and I'm not sure what other company has delivered a product with FinFETs yet.

Only Intel. I doubt you'll see a non-Intel product with FinFETs before H2 2015 or H1 2016.

 

[dopefish]

I'm not sure what you're saying here. FD-SOI is a new technology, there are no chips on the market that use it. The only products I'm aware of that have even been announced to use FD-SOI are from ST, the developers of the 28nm FD-SOI process. On the other hand, Samsung has announced that they will offer an FD-SOI variant of their 28nm process, so there is probably some kind of customer base for it. There have also been mentions of FD-SOI extending down to 20nm and 14nm, but who knows what will happen...


Some earlier processes used PD-SOI, but most don't (including anything from Intel or TSMC) - they use "bulk" processes instead. Past AMD products made at Global Foundries (their big CPU product lines) used PD-SOI, but even they are transitioning to bulk; the 28nm Kaveri is made on a bulk process.


As for needing FinFET below 28nm, TSMC, Samsung, and Global Foundries are all doing 20nm processes that don't incorporate FinFETs. But they don't offer as much of a performance advantage as earlier shrinks do, which is why they're transitioning to processes that incorporate FinFETs soon after - the ones they call 16nm or 14nm are actually using the same back-end-of-line geometry as the 20nm process, so they're not much denser.

Thank you for your thorough explanation. I believe I got my wording all confused. I suppose I was more or less referring to how Intel used more traditional fabrication in Sandy Bridge, which was 32nm, but went to a new fangled 3D tri-gate technology starting in Ivy Bridge, due to the possible inability to drop the node size down using the old method. I'm more of a software guy and less of a hardware guy, so you will have to excuse my occasional ignorance.

 

[Exophase]

Thank you for your thorough explanation. I believe I got my wording all confused. I suppose I was more or less referring to how Intel used more traditional fabrication in Sandy Bridge, which was 32nm, but went to a new fangled 3D tri-gate technology starting in Ivy Bridge, due to the possible inability to drop the node size down using the old method. I'm more of a software guy and less of a hardware guy, so you will have to excuse my occasional ignorance.

I think this is more or less on target. Intel decided that they couldn't get enough of a performance improvement going from 32nm to 22nm with planar geometry and moved to FinFETs. This is pretty much evident in what TSMC, Samsung, and GF are reporting - while they are offering 20nm planar nodes they're not that impressive outside of density improvement. And it seem like a lot of fabless companies are reluctant to transition to it at all, instead waiting for the versions with FinFETs.

FD-SOI solves some of the same problems that FinFETs do, but there are some other tradeoffs involved. There's a good article about it here: https://www.semiwiki.com/forum/content/2891-alternative-finfet-fd-soi.html

 

[_jr_]

Thanks for the link. Will be interesting to see what happens, if future processes actually get more expensive.