GP32 Arm Mode Questions


velvetfr

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Hi,

I experimented last night re. the different ARM modes (especially the User, System and Supervisor). I have noticed that GP32 gives Supervisor mode when entering any FXEs (I guess the same for GXEs), and then if you switch to user/system mode, setting a good stack pointer, then a lot of SWIs call make the GP32 crashing. I have attached a snippet of a such crash :

@ Switch to user mode, or system mode and disable IRQ and FIRQ
mov r0, #0xd0 @ same with 0xdf (system mode) ... works with 0xd3 (supervisor mode)
msr cpsr, r0
@ Set the stack pointer to a valid memory area
ldr sp, =0x0c6ffff0

@ Enable the video output
mov r2, #3
swi 0x8

Seems that the GP32 SWIs are not useable in user or system mode, but do not see really a good reason why not ....

Thanks,
velvetfr
 
Hi, i'm not sure how the SWI handling is written in the firmware.
SWIs is executed in supervisor mode, gamepark might have written some ugly code assuming the SWI was also called from supervisor mode.
Did you check the firmware dump at spiv site?


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mithris
 
Hi,

I have my own Firmware 1.57 dump, but as far as I see, the SWI's handler does not really extravagant things. Perhaps a hardware limitation as on GBA (supervisor mode cannot be reached, done by a hardware trick, as I remember correctly).

velvetfr
 
Hi,

I think I discovered the reason ... here a snippet of the SWI handler from the GP32 BIOS :

@ SWI handler
f0: e92d4003 stmdb sp!, {r0, r1, lr}
@ Disable IRQ
f4: e14f0000 mrs r0, SPSR
f8: e3801080 orr r1, r0, #128 ; 0x80
fc: e12ff001 msr CPSR_fsxc, r1

Just assume that the CPU has been set to system mode (the same would apply for the user mode too) ... at that point, the CPSR will be 0x000000df (assuming that IRQ and FIRQ is disabled) ... then
call a SWI, which will force the CPU to do tricks with PC and LR (but in that case, not important), and will also save the CPSR to SPSR_svc (=0x000000df) and force the CPU in supervisor mode (CPSR will be now 0x000000d3) .. then the problem will occur when the SWI handler is fetching the SPSR to disable the IRQ and replace CPSR by this new content, which will be 0x000000df (System mode), and now the SWI handler is not at all under supervisor mode, which will mess up with the registers and force the CPU to have an unknown behaviour.

That is the main reason that calling BIOS function through SWI will make you GP32 crazy when not calling them in supervisor mode, which is quite a shame ... so would it be a bug, or a 'feature', this is the question :eek:

velvetfr
 
I'd say a bug.. or well, it's the way gamepark decided to do stuff.
Much would have been easier if they only decided to run the applications in user or system mode.

But, what i wonder, is why they are fetching SPSR when disabling IRQ's.
And, according to the ARM ARM IRQ's is disabled when entering supervisor mode through a SWI.
So disabling IRQ's again would be pointless?
It seems odd indeed, but perhaps they did have a plan when they wrote that code..

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mithris
 
I'd say a bug.. or well, it's the way gamepark decided to do stuff.
Much would have been easier if they only decided to run the applications in user or system mode.

But, what i wonder, is why they are fetching SPSR when disabling IRQ's.
And, according to the ARM ARM IRQ's is disabled when entering supervisor mode through a SWI.
So disabling IRQ's again would be pointless?
It seems odd indeed, but perhaps they did have a plan when they wrote that code..

---
mithris
Hi,

yes it sounds more like a bug, you're right Mithris, but anyway, if someone want to benefit of the user/system modes, the BIOS has to be rewrote, or all the SWI calls have to be transformed to internal functions calls which does the same.

Nevertheless, not even sure if any projects on GP32 are using user/system mode :huh:

velvetfr
 
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Nevertheless, not even sure if any projects on GP32 are using user/system mode :huh:
None I know off.. for the obvious reason. The official SDK wouldn't survive even the first setup in gpstart.o if the crt0.o would switch the system to other than supervisor mode.
 
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