Am Thu, 6 Feb 2014 17:14:59 +0100 hat "Dr. H. Nikolaus Schaller" hns@goldelico.com geschrieben:
Hi,
I have worked through all documentation I have, to improve all the driver settings (but still not successful).
Okay - so time to ask TI or some other one who knows more about MIPI?
Some more observations:
- it is quite tricky to calculate the correct clock frequencies for
pixel clock, hs-lane clock and low-power clock - but I have packed that into (I hope) well documented macros
- one problem is that the MIPI data transmission must have some %
higher bandwidth than the display will generate (to add margin for framing and error correction)
- but the kernel appears to limit the MIPI clock to 450 MHz (which
appears to be ok for OMAP4 but OMAP5 should be able to run up to >600 MHz)
Does the kernel you're using support the OMAP5 or only the OMAP4? Could that be an issue here?
- anyways this can be addressed for the moment by making the pixel
clock slower (reducing the refresh rate to 50 Hz)
Well - do we know that the LCD support 50Hz? (we do hope so, but we don't know)
Well, although the panel frequencies appear to be ok:
[ 45.991607] DSI: Data rate on 1 DSI lane 864 Mbps [ 45.991607] DSI: Clock lane freq 432000000 Hz
[ 46.488250] DISPC: channel 0 xres 1080 yres 1920 [ 46.488281] DISPC: pck 120000 [ 46.488281] DISPC: hsw 10 hfp 10 hbp 100 vsw 10 vfp 10 vbp 60 [ 46.488281] DISPC: vsync_level 0 hsync_level 0 data_pclk_edge 1 de_level 0 sync_pclk_edge 0 [ 46.488311] DISPC: hsync 100000Hz, vsync 50Hz
the main symptom is still:
[ 3.641601] omapdss DSI error: DSI error, irqstatus 400a0 [ 3.647247] DSI: DSI IRQ: 0x400a0: RESYNC PLL_LOCK SYNC_LOST
[ 46.505615] omapdss DSI error: DSI error, irqstatus 401a0 [ 46.505615] DSI: DSI IRQ: 0x401a0: RESYNC PLL_LOCK PLL_UNLOCK SYNC_LOST
shortly (20ms) after the DSI panel reports successful power on.
Hm.... Sync lost... so the timings seem to be incorrect, I guess.
And I have added some code to read the actual_backlight intensity from the panel - but it gives a communication timeout. Note that this function should IMHO not need the high-speed clock to work (correctly):
A communication timeout would also happen if timings are not in sync, correct?
So either communication lines are not working properly or they are trying to communicate with different clockrates (which apparently would lead to a timeout).
root@gta04:~# root@cat /sys/devices/ocp.3/dss.10/0.dsi/display0/backlight/r63311/actual_brightness [ 67.482238] dsi: r63311_get_brightness() [ 67.980895] omapdss DSI error: Failed to receive BTA [ 67.986145] omapdss DSI error: dsi_vc_dcs_read(ch 1, cmd 0x52) failed [ 67.994049] r63311 display0: read cmd/reg(0) failed: -5 [ 67.999725] dsi: -5=r63311_read(00) [ 68.003417] dsi: read 0 0 root@gta04:~#
This means that the video data stream has some problems that must be within the OMAP.
I will now try two things: a) experiment without any display adapter (this should not make a difference) b) modify the display adapter to use a dedicated GPIO for the panel reset (currently it is shared with the I2C devices which may make problems when suspending the panel)
Okay.
The latest kernel source is in branch "pyra-mipi". (BTW: can we have some public GitWeb access to link to patches/branches?).
Right, forgot about that. It's now public (http://git.openpandora.org)
Are you planning to ask other guys (TI Support forums?) for help with that GIT?