Surprise Announcment Of 4Th Quarter 2010 Intel Soc


Uh...Clem

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Apr 11, 2010
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Man, they did a great job of keeping this a secret for something that's due to release so near-term! Still, an EE Times article states that it uses 3 watts, so it uses, what, about three times more power than the current TI OMAPs?:

Intel unveils Queensbay family of Atom microprocessors (SoCs)

"The first member of the Queensbay family is due out in the fourth quarter, a chip code-named Tunnel Creek. It will come in three flavors, 600MHz, 1.1GHz and 1.3GHz, and is a small package with most of the functions traditionally in the north and south bridge chipset all packed onto the same chip as the processor.

The main chip includes the processor; memory controller for 667MHz and 800MHz DDR2 (double data rate, second generation DRAM); a 3D graphics engine; high definition capable video decoder and video encoding engine as well as display controller with support for an additional display; a legacy peripheral controller; and a high-definition audio controller, all on one piece of silicon.

Tunnel Creek is 46 percent smaller than Menlow, Intel's previous chip package for the embedded market.

The new chip also includes PCI Express, the latest upgrade to PCI, which was vital to connect add-on cards such as video, audio and graphics to a PC's motherboard. PCI Express is speedier, works with more OSes and allows more add-ons. Some people have noted the importance of Intel using PCIe in a family of Atom chips because it's a widely used standard, and because Intel will not use PCIe in the new generation Atom processors aimed at netbooks, called Moorestown, which are due out in June."
 
I guess this is where things finally converge.. an x86 SoC that has greater power consumption and lower performance than the ARM cores that'll be out around the same time. Neat.

I also think PCI Express is going to be unappealing for the markets this should be targeting. This chip will be very unappealing in netbooks where the power saved won't make enough of a difference to warrant the performance reduction.
 
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