Exophase said:
"MIPS" stands for "millions of instructions per second." Unfortunately, companies have often said MIPS when they actually mean "DMIPS", or the result of the Dhrystone benchmark normalized against a score obtained on a VAX 11/780, a machine advertised as being capable of executing 1 million instructions per second (but actually typically performed at a much lower rate).
2 instructions per clock cycle is a theoretical maximum on Cortex-A8. In practice you'll rarely achieve anywhere close to this because of stalls that occur due to things like:
- Register dependencies preventing dual pipeline pairing pairing
- Register dependencies stalling operations with multiple cycle latencies like loads and multiplies
- Branch mispredictions
- L1 cache misses and worse, L2 cache misses
ARM has reported a typical throughput of only 0.9 instructions per cycle on their reference A8 implementation (tested over several "industry standard applications"). I would expect OMAP3's would be worse due to poor memory latency.
GFLOPS stands for giga floating point operations per second, and is a function of floating point operations per cycle and clock speed. With NEON, ARM is capable of performing two floating point operations per cycle, or four if you consider a multiply and accumulate instruction to be two operations (advertisements typically do). I say this in spite of NEON's very high MADD latency, which would make it hard to sustain full rate with. PSP, PS2, and Dreamcast, all having computational units designed for gaming, are capable of more FLOPs per clock cycle. The SGX on OMAP3 also has a FLOPs per cycle rate which I expect is 1 MADD per USSE (so two per cycle with SGX530), but it might be two MADDs per USSE instead.
I really do think it's awesome that you don't mind giving us extremely comprehensive answers like this. Unfortunately, I don't understand more than 50% of it (probably a lot less, actually) and I'm a third-year CS major.
I'll try to unpack this a bit, but keep in mind that I've never actually been taught any of this, I've mostly picked it up from reading your posts combined with half-remembered comments from other places, so I could be quite wrong (please correct me if this is the case and you don't mind taking the time):
- "Register dependencies preventing dual pipeline pairing pairing" : a CPU can only execute more than one instruction per cycle if the instructions don't each affect the same registers, so if they do, the instructions can't be scheduled together.
- "Register dependencies stalling operations with multiple cycle latencies like loads and multiplies" - if an operation affecting a particular register or set of registers takes more than one cycle to execute, those registers can't be used for other operations in the meantime.
- "Branch mispredictions" - when filling the pipeline modern CPUs can assess the probabilities of the results of particular instructions, but if they predict the results of a branch incorrectly, the pipeline has to be flushed and refilled from another location.
- "L1 cache misses and worse, L2 cache misses" - CPUs store frequently-accessed data and instructions in cache on the CPU die, which has the advantage of very fast access times, but if it encounters the need to load data that isn't in the cache, it has to load it from main memory, which can take hundreds of cycles.
Am I generally correct here?
lulzfish seems to do a good job explaining the rest.
